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MC74VHC125 Quad Bus Buffer
with 3-State Control Inputs
The MC74VHC125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC125 requires the 3-state control input (OE) to be set High to place the output into the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
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* * * * * * * * * * *
High Speed: tPD = 3.8ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM Active-Low Output Enables
A1 OE1 A2 OE2 A3 OE3 A4 OE4 2 1 5 4 9 10 12 13 11 8 Y3 6 3 Y1
14-LEAD SOIC D SUFFIX CASE 751A
14-LEAD TSSOP DT SUFFIX CASE 948G
14-LEAD SOIC EIAJ M SUFFIX CASE 965
PIN CONNECTION AND MARKING DIAGRAM (Top View)
OE1 A1 Y1 OE2 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC OE4 A4 Y4 OE3 A3 Y3
Y2
For detailed package marking information, see the Marking Diagram section on page 5 of this data sheet.
ORDERING INFORMATION
Device Y4 MC74VHC125D MC74VHC125DT Package SOIC TSSOP SOIC EIAJ Shipping 55 Units/Rail 96 Units/Rail 50 Units/Rail
FUNCTION TABLE
VHC125 Inputs A H L X OE L L H Output Y H L Z
MC74VHC125M
(c) Semiconductor Components Industries, LLC, 2000
1
April, 2000 - Rev. 2
Publication Order Number: MC74VHC125/D
MC74VHC125
II I III I II II I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage DC Input Voltage Value Unit - 0.5 to + 7.0III V - 0.5 to + 7.0III V V Vout IIK DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 50 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW Tstg - 65 to + 150
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
v
v
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
Symbol VCC Vin Parameter Min 2.0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage Vout TA DC Output Voltage VCC + 85 100 20 Operating Temperature, All Package Types Input Rise and Fall Time - 40 0 0
_C
tr, tf
VCC = 3.3V 0.3V VCC =5.0V 0.5V
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH Parameter Minimum High-Level Input Voltage
VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5
TA = 25C Typ
TA 85C Min 1.5 2.1 3.15 3.85 Max
TA 125C Min 1.5 2.1 3.15 3.85 Max Unit V
Test Conditions
Min 1.5 2.1 3.15 3.85
Max
VIL
Maximum Low-Level Input Voltage
0.5 0.9 1.35 1.65 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.25 2.0 3.0 4.5 1.9 2.9 4.4 2.48 3.80
0.5 0.9 1.35 1.65 1.9 2.9 4.4 2.34 3.66 0.1 0.1 0.1 0.44 0.44 2.5
0.5 0.9 1.35 1.65
V
VOH
Minimum High-Level Output Voltage VIN = VIH or VIL
VIN = VIH or VIL IOH = -50A VIN = VIH or VIL IOH = -4mA IOH = -8mA
2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5
V
V
VOL
Maximum Low-Level Output Voltage VIN = VIH or VIL
VIN = VIH or VIL IOL = 50A VIN = VIH or VIL IOL = 4mA IOL = 8mA
0.1 0.1 0.1 0.52 0.52 2.5
V
V
IOZ
Maximum 3-State Leakage Current
VIN = VIH or VIL VOUT = VCC or GND
A
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MC74VHC125
IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current VIN = 5.5V or GND VIN = VCC or GND 0 to 5.5 5.5 0.1 4.0 1.0 40 1.0 40 A A
II I I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I I I I I I I IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II IIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Parameter Test Conditions TA = 25C Typ 5.6 8.1 3.8 5.3 5.4 7.9 3.6 5.1 9.5 6.1 TA = 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 TA = 125C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max Min Max 8.0 11.5 5.5 7.5 Max Unit ns Maximum Propagation Delay, A to Y VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V (Note 1.) VCC = 5.0 0.5V (Note 1.) CL = 15pF CL = 50pF CL = 15pF CL = 50pF 9.5 13.0 6.5 8.5 12.0 16.0 8.5 10.5 11.5 15.0 7.5 9.5 tPZL, tPZH Maximum Output Enable TIme, OE to Y CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 8.0 11.5 5.1 7.1 9.5 13.0 6.0 8.0 ns tPLZ, tPHZ Maximum Output Disable Time, OE to Y 13.2 8.8 1.5 1.0 10 15.0 10.0 1.5 1.0 10 18.0 12.0 1.5 1.0 10 ns tOSLH, tOSHL Output-to-Output Skew ns Cin Maximum Input Capacitance 4 6 pF pF Cout Maximum Three-State Output Capacitance (Output in High Impedance State) Typical @ 25C, VCC = 5.0V 14 CPD Power Dissipation Capacitance (Note 2.) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.3 - 0.3 Max 0.8 - 0.8 3.5 1.5 Unit V V V V
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MC74VHC125
SWITCHING WAVEFORMS
VCC GND tPZL tPLZ Y 50% VCC tPZH tPHZ Y 50% VCC HIGH IMPEDANCE VOL + 0.3V VOH - 0.3V HIGH IMPEDANCE
OE VCC 50% A tPLH 50% VCC Y tPHL GND
50%
Figure 1.
Figure 2.
TEST POINT OUTPUT DEVICE UNDER TEST
TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
DEVICE UNDER TEST
CL *
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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MC74VHC125
MARKING DIAGRAMS (Top View)
14 13 12 11 10 9 8 14 13 12 11 10 9 8
VHC125 AWLYWW*
1 2 3 4 5 6 7 1 2 3
VHC 125 ALYW*
4 5 6 7
14-LEAD SOIC D SUFFIX CASE 751A 14 13 12 11 10 9 8
14-LEAD TSSOP DT SUFFIX CASE 948G
VHC125 AWLYWW*
1 2 3 4 5 6 7
14-LEAD SOIC EIAJ M SUFFIX CASE 965
*See Applications Note #AND8004/D for date code and traceability information.
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MC74VHC125
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL
0.25 (0.010)
M
B
M
G C
R X 45
F
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K T B
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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CCC EE CCC EE
SECTION N-N -W-
MC74VHC125
PACKAGE DIMENSIONS
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHC125
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MC74VHC125/D

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